A PLL is equipped in an RF transmitter/receiver as a synthesizer which generates a high-frequency clock being phase-synthesized to a reference clock. An RF (high frequency) transmitter/receiver requires a local oscillation clock with low noise, which is stable in high-frequency (for example, GHz) bands. A PLL synthesizer for generating such a local oscillation clock is required to generate a high-frequency clock with less jitter, of which the frequency is stable.
A PLL synthesizer includes, a phase frequency comparator which performs a comparison of phases of a reference clock and a feedback clock fed back from an output clock, a charge-pump circuit which generates current according to the phase comparison result, a loop filter which generates a control voltage according to the current of the charge-pump circuit, a voltage controlled oscillator which oscillates by a frequency according to the control voltage, and a divider which divides an output clock generated by the voltage controlled oscillator.
Related descriptions are disclosed in Japanese patent laid-open publications No. 2000-188542, and No. 2007-266935.
For equipping a PLL synthesizer on a CMOS high-frequency LSI, it is desired, for reducing power consumption and area, to reduce the current of the charge-pump circuit and the R/C constant of the loop filter.
However, if the current of the charge pump is reduced, unbalance between a push current as a positive charge current and a pull current as a negative charge current increases, and, because of the resistance or capacitance of the loop filter being reduced, a control voltage generated by the loop filter varies widely, thus causing more jitter of the output clock (fluctuation of the phase). Also, on a chip where an LSI is formed, characteristics of the loop filter or the voltage oscillator become non-linear characteristics differing from ideal characteristics thereof, and thus cause the jitter of the output clock.
Since an output clock of a PLL synthesizer equipped on an RF transmitter/receiver is used as a local clock for a down-converting mixer, increase of jitter of the output clock, which is phase fluctuation, is not permissible.
Further, if loop gain of a PLL loop decreases due to a limitation to the current of the charge-pump circuit, fluctuation of characteristics of the loop filter or the voltage controlled oscillator is likely to influence the PLL loop characteristic. Since loop filter and voltage controlled oscillator formed in a chip have characteristics differing from the ideal characteristics thereof, influence thereby to the PLL loop characteristic becomes unignorable.